//########################################################################### // // FILE: //
// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions. //
//########################################################################### // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ // $Release Date: August 4, 2009 $ //###########################################################################
#include \"DSP2833x_Device.h\" // DSP2833x Headerfile Include File #include \"DSP2833x_Examples.h\" // DSP2833x Examples Include File
DSP2833x_ECan.c
DSP28335文库源代码系列1：
一：说明：
DSP28335 ECAN测试：
声明：由于不能上传代码，故将can通讯测试程序整理到word文档，大家可以参考，并配有实验结果，只需要简单的移植既可以使用，请勿盗版！
上图为参考C文件，在官方例程中都有，下面贴出重要C文件的代码。
//--------------------------------------------------------------------------- // InitECan:
//---------------------------------------------------------------------------
// This function initializes the eCAN module to a known state. //
void InitECan(void) {
InitECana(); #if DSP28_ECANB
二：代码部分
两个主要C文件的代码，其他C文件大家自己添加就可以了，本部分程序是AB 两个can口之间相互通讯，如果需要源代码，可以发我：letchgo@163.
DSP2833x_ECan：
// TI File $Revision: /main/8 $ // Checkin $Date: June 25, 2008 15:19:07 $
Word文档资料
.
InitECanb();
#endif // if DSP28_ECANB }
void InitECana(void) // Initialize
eCAN-A module {
/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is
allowed to these registers. 16-bit access to these registers could potentially corrupt the register contents or return false data. This is especially true while writing to/reading from a bit
(or group of bits) among bits 16 - 31 */
struct ECAN_REGS ECanaShadow;
EALLOW; //
EALLOW enables access to protected bits
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
ECanaShadow.CANTIOC.all =
ECanaRegs.CANTIOC.all;//配置GPIO引脚为CAN通讯
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
Word文档资料
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ // HECC mode also enables time-stamping feature事件抽样特征
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
.
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000; Word文档资料
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again // as a matter of precaution.
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all =
0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all =
0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
.
ECanaShadow.CANES.all = ECanaRegs.CANES.all; do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
}
while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
#if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
See Note at End of File */
ECanaShadow.CANBTC.bit.BRPREG = 4;
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
ECanaShadow.CANBTC.bit.TSEG1REG = 10; #endif
#if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
See Note at End of File */
Word文档资料
ECanaShadow.CANBTC.bit.BRPREG = 4; ECanaShadow.CANBTC.bit.TSEG2REG = 1;
ECanaShadow.CANBTC.bit.TSEG1REG = 6; #endif
ECanaShadow.CANBTC.bit.SAM = 1; ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANES.all = ECanaRegs.CANES.all; do {
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
}
while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
.
EDIS; }
#if (DSP28_ECANB) void InitECanb(void) // Initialize
eCAN-B module {
/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is
allowed to these registers. 16-bit access to these registers could potentially corrupt the register contents or return false data. This is especially true while writing to/reading from a bit
(or group of bits) among bits 16 - 31 */
struct ECAN_REGS ECanbShadow;
EALLOW; // EALLOW enables access to protected bits
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
ECanbShadow.CANTIOC.bit.TXFUNC = 1;
ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;
ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; Word文档资料
ECanbShadow.CANRIOC.bit.RXFUNC = 1;
ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.SCB = 1;
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
.
ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000; Word文档资料
ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again // as a matter of precaution.
ECanbRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanbRegs.CANRMP.all =
0xFFFFFFFF; /* Clear all RMPn bits */
ECanbRegs.CANGIF0.all =
0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanbRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANB*/
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
.
ECanbShadow.CANES.all = ECanbRegs.CANES.all; do
{
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
}
while(ECanbShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be cleared..
ECanbShadow.CANBTC.all = 0;
#if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
See Note at end of file */
ECanbShadow.CANBTC.bit.BRPREG = 4;
ECanbShadow.CANBTC.bit.TSEG2REG = 2;
ECanbShadow.CANBTC.bit.TSEG1REG = 10;
#endif
#if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
See Note at end of file */
Word文档资料
ECanbShadow.CANBTC.bit.BRPREG = 4; ECanbShadow.CANBTC.bit.TSEG2REG = 1;
ECanbShadow.CANBTC.bit.TSEG1REG = 6; #endif
ECanbShadow.CANBTC.bit.SAM = 1; ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
ECanbShadow.CANES.all = ECanbRegs.CANES.all; do {
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
}
while(ECanbShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs
.
EDIS; }
#endif // if DSP28_ECANB
//---------------------------------------------------------------------------
// Example: InitECanGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as eCAN pins //
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO // inputs after reset. //
// Caution:
// Only one GPIO pin should be enabled for CANTXA/B operation.
// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
// Comment out other unwanted lines.
void InitECanGpio(void) {
InitECanaGpio(); InitECanbGpio(); #if (DSP28_ECANB) InitECanbGpio();
Word文档资料
#endif // if DSP28_ECANB }
void InitECanaGpio(void) {
EALLOW;
/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
//GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA)
//GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (CANTXA)
/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
.
//GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA) GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA)
/* Configure eCAN-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.
//GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA operation
//GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA operation EDIS; }
#if (DSP28_ECANB) void InitECanbGpio(void) {
EALLOW;
/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
Word文档资料
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
//GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up for GPIO8 (CANTXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up for GPIO12 (CANTXB) GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up for GPIO16 (CANTXB) // GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up for GPIO20 (CANTXB)
//GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10 (CANRXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13 (CANRXB) GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17 (CANRXB) // GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21 (CANRXB)
/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
// GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB) // GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB) GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
.
// GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)
/* Configure eCAN-B pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.
//GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB operation
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB operation
//GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB operation
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB operation EDIS; }
#endif // if DSP28_ECANB /*
Word文档资料
Note: Bit timing parameters must be chosen based on the network parameters such
as the sampling point desired and the propagation delay of the network. The propagation delay is a function of length of the cable, delay introduced by the transceivers and opto/galvanic-isolators (if any).
The parameters used in this file must be changed taking into account the above mentioned factors in order to arrive at the bit-timing parameters suitable for a network. */
.
Example_2833xEcanA_to_B_Xmit：
// TI File $Revision: /main/9 $
// Checkin $Date: April 21, 2008 15:41:13 $ //########################################################################### // Filename:
Example_28xEcan_A_to_B_Xmit.c //
// Description: eCAN-A To eCAN-B TXLOOP - Transmit loop //
// ASSUMPTIONS: //
// This program requires the DSP2833x header files. //
// Both CAN ports of the 2833x DSP need to be connected
Word文档资料
// to each other (via CAN transceivers) //
// eCANA is on GPIO31 (CANTXA) and // GPIO30 (CANRXA) //
// eCANB is on GPIO8 (CANTXB) and // GPIO10 (CANRXB) //
// As supplied, this project is configured for \"boot to SARAM\"
// operation. The 2833x Boot Mode table is shown below.
// For information on configuring the boot mode of an eZdsp,
// please refer to the documentation included with the eZdsp, //
// $Boot_Table: //
// GPIO87 GPIO86 GPIO85 GPIO84 // XA15 XA14 XA13 XA12 // PU PU PU PU
//
==========================================
// 1 1 1 1 Jump to Flash // 1 1 1 0 SCI-A boot // 1 1 0 1 SPI-A boot // 1 1 0 0 I2C-A boot // 1 0 1 1 eCAN-A boot // 1 0 1 0 McBSP-A boot // 1 0 0 1 Jump to XINTF x16
.
// 1 0 0 0 Jump to XINTF x32
// 0 1 1 1 Jump to OTP // 0 1 1 0 Parallel GPIO I/O boot
// 0 1 0 1 Parallel XINTF boot
// 0 1 0 0 Jump to SARAM <- \"boot to SARAM\"
// 0 0 1 1 Branch to check boot mode
// 0 0 1 0 Boot to flash, bypass ADC cal
// 0 0 0 1 Boot to SARAM, bypass ADC cal
// 0 0 0 0 Boot to SCI-A, bypass ADC cal
// Boot_Table_End$ //
// DESCRIPTION: //
// This example TRANSMITS data to another CAN module using MAILBOX5 // This program could either loop forever or transmit \"n\" # of times,
// where \"n\" is the TXCOUNT value. //
// This example can be used to check CAN-A and CAN-B. Since CAN-B is // initialized in DSP2833x_ECan.c, it will acknowledge all frames
// transmitted by the node on which this code runs. Both CAN ports of
// the 2833x DSP need to be connected to each other (via CAN transceivers) //
Word文档资料
//########################################################################### // Original Author: HJ //
// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $
// $Release Date: August 4, 2009 $
//###########################################################################
#include \"DSP28x_Project.h\" // Device Headerfile and Examples Include File
#define TXCOUNT 100 // Transmission will take place (TXCOUNT) times..
// Globals for this example long i; long
loopcount = 0;
extern void test(void); void CanB_Config(void); void main() {
/* Create a shadow register structure for the CAN control registers. This is
needed, since, only 32-bit access is allowed to these registers. 16-bit access to these registers could potentially corrupt the register contents. This is
especially true while writing to a bit (or group of bits) among bits 16 - 31 */ test();
struct ECAN_REGS ECanaShadow;
.
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks // This example function is found in the DSP2833x_SysCtrl.c file. InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped 1for this example
// Just initalize eCAN pins for this example // This function is in DSP2833x_ECan.c InitECanGpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags // are cleared.
// This function is found in the DSP2833x_PieCtrl.c file. InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
Word文档资料
IER = 0x0000; IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt // Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c. // This function is found in DSP2833x_PieVect.c. InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
// No interrupts used in this example.
// Step 4. Initialize all the Device Peripherals: // This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// In this case just initalize eCAN-A and eCAN-B
// This function is in DSP2833x_ECan.c InitECan();
// Step 5. User specific code:
.
/* Write to the MSGID field */
ECanaMboxes.MBOX25.MSGID.all =
0x95555555; // Extended Identifier扩展标示符，标示符寄存器
/* Configure Mailbox under test as a Transmit mailbox */
ECanaShadow.CANMD.all =
ECanaRegs.CANMD.all;//方向寄存器CANMD，用于配置以进行发送或接受操作 ECanaShadow.CANMD.bit.MD25 = 0;//CANA的第25个为0配置为发送 ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
/* Enable Mailbox under test */
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME25 = 1; ECanaRegs.CANME.all =
ECanaShadow.CANME.all;//激活寄存器，25被激活为RAM模式
/* Write to DLC field in Master Control reg */
ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8;//发送字节数的位数为8
/* Write to the mailbox RAM field */
ECanaMboxes.MBOX25.MDL.all = 0x10000; ECanaMboxes.MBOX25.MDH.all = 0xff555555;//存储CAN消息的数据域
Word文档资料
/* Begin transmitting */ CanB_Config();
for(i=0;; i++) {
ECanaShadow.CANTRS.all = 0;
ECanaShadow.CANTRS.bit.TRS25 = 1; // Set TRS for mailbox under test
ECanaRegs.CANTRS.all =
ECanaShadow.CANTRS.all;//发送请求置位寄存器 do
{
ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
}
while(ECanaShadow.CANTA.bit.TA25 == 0 ); // Wait for TA5 bit to be set..发送应答寄存器，消息成功发送则置位1
ECanaShadow.CANTA.all = 0; ECanaShadow.CANTA.bit.TA25 = 1; // Clear TA5 ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;
loopcount ++; }
asm(\" ESTOP0\"); // Stop here }
void test(void) {loopcount=2567809;}
.
void CanB_Config(void) { struct ECAN_REGS ECanbShadow;
/* Write to the MSGID field */
ECanbMboxes.MBOX26.MSGID.all = 0x95555555; // Extended Identifier扩展标示符，标示符寄存器
/* Configure Mailbox under test as a Transmit mailbox */
ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;//方向寄存器CANMD，用于配置以进行发送或接受操作 ECanbShadow.CANMD.bit.MD26 = 1;//CANA的第25个为0配置jieshou ECanbRegs.CANMD.all = ECanbShadow.CANMD.all; /* Enable Mailbox under test */
ECanbShadow.CANME.all = ECanbRegs.CANME.all; ECanbShadow.CANME.bit.ME26 = 1;
ECanbRegs.CANME.all =
ECanbShadow.CANME.all;//激活寄存器，25被激活为RAM模式
/* Write to DLC field in Master Control reg */
ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8;//发送字节数的位数为8
Word文档资料
/* Write to the mailbox RAM field */
}
三：测试记录：
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