DG535_08资料

DG535/536

Vishay Siliconix

16-Channel Wideband Video Multiplexers

DESCRIPTION

The DG535/536 are 16-channel multiplexers designed forrouting one of 16 wideband analog or digital input signals toa single output. They feature low input and outputcapacitance, low on-resistance, and n-channel DMOS “T”switches, resulting in wide bandwidth, low crosstalk and high“off” isolation. In the on state, the switches pass signals ineither direction, allowing them to be used as multiplexers oras demultiplexers.

On-chip address latches and decode logic simplifymicroprocessor interface. Chip Select and Enable inputssimplify addressing in large matrices. Single-supplyoperation and a low 75 µW power consumption vastlyreduces power supply requirements.

Theses devices are built on a proprietary D/CMOS processwhich creates low-capacitance DMOS FETs andhigh-speed, low-power CMOS logic on the same substrate.For more information please refer to Vishay SiliconixApplication Note AN501 (FaxBack document number70608).

FEATURES

• • • • • • •

Crosstalk: - 100 dB at 5 MHz300 MHz Bandwidth

Low Input and Output CapacitanceLow Power: 75 µWLow rDS(on): 50 Ω

On-Board Address LatchesDisable Output

Pb-freeAvailableRoHS*COMPLIANTBENEFITS

• • • • •

High Video Quality

Reduced Insertion Loss

Reduced Input Buffer RequirementsMinimizes Power ConsumptionSimplifies Bus Interface

APPLICATIONS

• • • • • •

Video Switching/RoutingHigh Speed Data RoutingRF Signal MultiplexingPrecision Data AcquisitionCrosspoint ArraysFLIR Systems

FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION

GNDS8S7S6S5S4S3S2S1DISCSCSENA01234567101112Latches/Decoders/Drivers1314Top ViewDual-In-LineTop View1615DG535DG536282726252423222120191817S9GNDGNDS1S10S11S12S13S14S15S16DV+STA3S16GNDS15GNDS14GNDS13GNDS12GNDGNDA2A11819202122232425262728DISCSCSENA0A1A2A3STV+D71011121314151617Latches/Decoders/Drivers3938373635343332313029S6GNDS7GNDS8GNDS9GNDS10GNDS11PLCC/CerquadGNDGNDS4GNDS5GNDS2S363214443424140* Pb containing terminations are not RoHS compliant, exemptions may applyDocument Number: 70070S-71241–Rev. E, 25-Jun-07

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DG535/536

Vishay Siliconix

ORDERING INFORMATION

Temperature Range

- 40 to 85 °C

44-Pin PLCCPackage28-Pin Plastic DIP

Part NumberDG535DJDG535DJ-E3DG536DNDG536DN-E3

TRUTH TABLE

EN0XXCSX0XCSXX1STa1

A3X0000000011111111X

A2X0000111100001111X

A1X0011001100110011X

A0X0101010101010101X

Channel Selected

None

S1S2S3S4S5S6S7S8S9S10S11S12S13S14S15S16

Maintains previous switch condition

DisablebHigh Z

1101Low Z

XXXLogic \"0\" = VAL ≤ 4.5 VLogic \"1\" = VAH ≥ 10.5 VX = Do not Care

0High Z or Low Z

Notes:

a. Strobe input (ST) is level triggered.

b. Low Z, High Z = impedance of Disable Output to GND. Disable output sinks current when any channel is selected.

ABSOLUTE MAXIMUM RATINGS

Parameter V+ to GNDDigital InputsVS, VD

Current (any terminal) Continuous Current (S or D) Pulsed 1 ms 10 % duty cycle(A Suffix)

Storage Temperature

(D Suffix)Power Dissipation (Package)a

28-Pin Plastic DIPb28-Pin Sidebrazec44-Pin PLCCd44-Pin CerquadeLimit- 0.3 to + 18

(GND - 0.3) to (V+) + 2

or 20 mA, whichever occurs first

(GND - 0.3) to (V+) + 2

or 20 mA, whichever occurs first

2040- 65 to 150- 65 to 125

6251200450825Unit

V

mA°C

mW

Notes:

a. All leads soldered or welded to PC board.b. Derate 8.6 mW/°C above 75 °C.c. Derate 16 mW/°C above 75 °C.d. Derate 6 mW/°C above 75 °C.e. Derate 11 mW/°C above 75 °C.

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DG535/536

Vishay Siliconix

SPECIFICATIONSa

Test Conditions Unless Otherwise Specified V+ = 15 V, ST, CS = 10.5 V

CS = 4.5 V, VA = 4.5 or 10.5 Vfarameter Symbol Analog Switch

VANALOGAnalog Signal RangeeDrain-Source

On-ResistanceResistance Match

Source Off Leakage CurrentDrain On Leakage CurrentDisable OutputDigital ControlInput Voltage HighInput Voltage LowAddress Input CurrentAddress Input CapacitanceDynamic Characteristics

PLCC

On State Input Capacitance

e

A Suffix - 55 to 125 °C

Tempb TypcFullRoomFullRoomRoomFullRoomFullRoomFullFull

55

Minc0

Maxc1090120910100101000200250

D Suffix - 40 to 85 °CMinc0

Maxc1090120910100- 10- 100200250

Unit VΩ

rDS(on)ΔrDS(on)IS(off)ID(on)RDISABLEVAIHVAILIAICA

IS = - 1 mA, VD = 3 V, EN = 10.5 V

Sequence Each Switch OnVS = 3 V, VD = 0 V, EN = 4.5 VVS = VD = 3 V, EN = 10.5 VIDISABLE = 1 mA, EN = 10.5 V

- 10- 100- 10- 1000

100

- 10- 100- 10- 100

nA

Ω

10.5

< 0.01532302538129

300

25

300150

- 35- 100- 93- 60- 85- 84- 60- 92- 87- 72- 74- 74- 60500

- 60

2055845

- 1- 100

4.51100

10.5- 1- 100

4.51100

VA = GND or V+

FullRoomFullFullRoomRoomRoomRoomRoomRoomRoomRoomRoomFullFullFullFullRoom

PLCCCerquadDIP

RoomRoomRoomRoomRoomRoomRoomRoomRoomRoomRoomRoomRoom

VµApF45558

pF

20

CS(on)VD = VS = 3 VCerquadDIPPLCC

POff State Input CapacitanceeCS(off)VS = 3 VCerquadDIPPLCC

Off State Output Capacitancee

Multiplexer Switching TimeBreak-Before-Make IntervalEN, CS, CS, ST, tONEN, CS, CS, ST, tOFFCharge Injection

Single-Channel Crosstalk

CD(off)tTRANStOPENtONtOFFQXTALK(SC)

VD = 3 VCerquadDIP

See Figure 4See Figure 2 and 3See Figure 2See Figure 5

RIN = 75 Ω, RL = 75 Ω

f = 5 MHzSee Figure 9

300

25

300150

pCns

Chip Disabled CrosstalkXTALK(CD)

Adjacent Input CrosstalkXTALK(AI)

RIN = RL = 75 Ω, f = 5 MHz PLCC

CerquadEN = 4.5 V

See Figure 8DIP

PLCCRIN = 10 Ω, RL = 10 kΩ

f = 5 MHz

See Figure 10RIN = 10 Ω, RL = 10 kΩ

f = 5 MHz See Figure 7

CerquadDIPPLCCCerquadDIP

dB

- 60

All Hostile CrosstalkeBandwidth

XTALK(AH)

BW

RL = 50 Ω, See Figure 6MHz

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DG535/536

Vishay Siliconix

SPECIFICATIONSa

Test Conditions Unless Otherwise Specified V+ = 15 V, ST, CS = 10.5 V

CS = 4.5 V, VA = 4.5 or 10.5 Vfarameter Symbol Power SuppliesPositive Supply CurrentSupply Voltage Range

I+V+

Any One Channge I Selected with All

Logic Inputs at GND or V+

Tempb TypcRoomFullFullFull

See Figure 1

FullFull

51020010050

A Suffix - 55 to 125 °CMinc

Maxc5010016.5

D Suffix - 40 to 85 °CMinc

Maxc5010016.5

Unit µAV

1020010050

Minimum Input Timing Requirements

tSWStrobe Pulse WidthA0, A1, A2, A3 CS, CS, ENData Valid to StrobeA0, A1, A2, A3 CS, CS, ENData Valid after Strobe

tDWtWD

ns

Notes:

a. Refer to PROCESS OPTION FLOWCHART.

b. Room = 25 °C, Full = as determined by the operating temperature suffix.

c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.e. Guaranteed by design, not subject to production test.f. VA = input voltage to perform proper function.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

400rDS(on)– Drain-Source On-Resistance (Ω)rDS(on)– Drain-Source On-Resistance (Ω)360320280240200160120804000246810VD – Drain Voltage (V)- 55 °C25 °C125 °CV+ = +15 VGND = 0 V30027024021018015012090603000246810VD – Drain Voltage (V)8 V12 V15 VGND = 0 VTA = 25 °CrDS(on) vs. VD and TemperaturerDS(on) vs. VD and Power Supply Voltagewww.vishay.com4Document Number: 70070S-71241–Rev. E, 25-Jun-07

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DG535/536

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

10987Vth(V)6321081012141618V+ – Positive Supply (V)20101112131415161718V+ – Positive Supply (V)I+ (µA)GND = 0 VTA = 25 °C141210125 °C8- 55 °C25 °CGND = 0 VLogic Input Switching Threshold

vs. Supply Voltage (V+)

1 µA100 nA10 nAV+ = + 15 VGND = 0 VVD = VS = 3 VIS, ID– Leakage 1 µA100 nA10 nASupply Current vs.

Supply Voltage and Temperature

V+ = + 15 VGND = 0 VID(off)IS(off)ID(on)– Leakage1 nA100 pA10 pA1 nA100 pA10 pA1 pA- 55- 35-1552565851051251 pA- 55-35-155256585105125Temperature (°C)Temperature (°C)ID(on) vs. Temperature

-120DG536RIN = 10 Ω-40Leakage Current vs. Temperature

-100DG536XTALK(AI)(dB)-80DG536RIN = 75 ΩInsertion Loss (dB)-8-3 dB Points-12Test CircuitSee Figure 6RL = 50 Ω-60DG535RIN = 10 Ω-40-16-20Test CircuitSee Figure 10-200.11101001DG5350f – Frequency (MHz)101001000f – Frequency (MHz)Adjacent Input Crosstalk vs. Frequency- 3 dB Bandwidth Insertion Loss vs. Frequency

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DG535/536

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

-160-140-120XTALK(CD)(dB)XTALK(AH)(dB)-100-80-60-40-2000.1110100f – Frequency (MHz)DG535RL = 75 ΩDG536RL = 75 ΩTest CircuitSee Figure 8-160-140-120-100-80-60-40-2000.1110100f – Frequency (MHz)Test CircuitSee Figure 7DG536RIN = 10 ΩRL = 10 kΩDG536RIN = 75 ΩRL = 75 ΩDG535RIN = 10 ΩRL = 10 kΩDG536RL = 50 ΩChip Disable Crosstalk vs. Frequency160140120Switching Time (ns)XTALK(SC)(dB)100806040200-55-35-155256585105125Temperature (°C)tOFFtBBMTest CircuitSee Figures 2, 3, 4tON-160-140-120-100-80-60-40-2000.1All Hostile Crosstalk vs. FrequencyTest CircuitSee Figure 9RIN = 75 ΩRL = 75 ΩDG536DG535110100f – Frequency (MHz)tON, tOFF and Break-Before-Make vs. TemperatureSingle Channel Crosstalk vs. FrequencyINPUT TIMING REQUIREMENTS

15 VST0 VtSWtDW15 V10.5 VCS, A0, A1, A2, A3CS, EN4.5 V0 V4.5 V10.5 VtWD7.5 VFigure 1.

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DG535/536

Vishay Siliconix

TEST CIRCUITS

+ 15 V+ 15 VLogicInputSTA0A1A2A3V+S16S1-S15+ 3 VAddressLogic Inputtr < 20 nstf < 20 ns15 V50 %0 VCSEN or CS 90 %D1 kΩ35 pFVOSignalOutputEN or CSCSGNDtONtOFFFigure 2. EN, CS, CS, Turn On/Off Time+ 15 V+ 15 VV+EN, CSA1, A2, A3AddressInputLogicInputA0STGNDCSAddressLogic Inputtr < 20 nstf < 20 nsS1+ 3 V15 V0 V15 V0 V50 %S2 - S15D1 kΩ35 pFVOVOUTtON(ST)90 %0 VFigure 3. Strobe ST Turn On Time

+ 15 V+ 15 V+ 3 VAddressLogic Inputtr < 20 nstf < 20 ns15 V50 %0 VSwitchOutputS1Turning OffDVO1 kΩ35 pF90 %S16Turning OnV+ENCSSTA0A1A2A3S1S16S2 thru S15GNDCStBBMtTRANSFigure 4. Transition Time and Break-Before-Make Interval

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DG535/536

Vishay Siliconix

TEST CIRCUITS

+ 15 V+ 15 VV+A0, A1, A2, A3S16CSGNDCSV+S2 thru S15STEN+ 3 VLogicInputDVOCL1000 pF+ 15 V+ 15 V+ 15 VCSENCSSTS1SignalGenerator(75 Ω)DA0toA3RL50 WVOVOUTΔVOUTGNDCSΔVOUT is the measured voltage error due to charge injection.The charge injection in Coulombs is Q = CL x ΔVOUTFigure 5. Charge Injection

Figure 6. Bandwidth

Channel 1 OnS1S2RINS3S4S5S6S7S8S9S10S11S12S13S14S15S16VVORLVOS1S2S3S4S5S6S7S8S9S10S11S12S13S14S15S16VAll Channels OffVORLXTALK(AH)= 20log10VVOXTALK(CD)= 20log10VFigure 7. All Hostile Crosstalk

Figure 8. Chip Disabled Crosstalk

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DG535/536

Vishay Siliconix

TEST CIRCUITS

Channel 1 OnS1S2RINS3S4S5S6S7S8S9S10VS11S12S13S14S15S16Notes:1. Any individual channel between S2 and S16 can be selectedisscannedsequentiallyfromS2toS162.XTALK(SC)= 20log10VVOXTALK(AI)= 20log10VSn–1VSnor20log10VSn+1VSnVSn+1RIN10 ΩSn+1RL10 kΩRLVSnSnVORIN10 ΩVSn–1Sn–1Figure 9. Single Channel CrosstalkFigure 10. Adjacent Input Crosstalk

PIN DESCRIPTION

SymbolS1 thru S16

D DIS CS, CS, EN A0 thru A3

ST V+ GND

Analog inputs/outputs

Multiplexer output/demultiplexer input

Open drain low impedance to analog ground when any channel is selected

Logic inputs to selected desired multiplexer(s) when using several multiplexers in a system Binary address inputs to determine which channel is selected Strobe input that latches A0, A1, A2, A3, CS, CS, EN Positive supply voltage input

Analog signal ground and most negative potential

All ground pins should be connected externally to ensure dynamic performance

Description

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DG535/536

Vishay Siliconix

DETAILED DESCRIPTION

The DG535/536 are 16-channel single-ended multiplexerswith on-chip address logic and control latches.

The multiplexer connects one of sixteen inputs (S1, S2through S16) to a common output (D) under the control of a4-bit binary address (A0 to A3). The specific input channelselected for each address is given in the Truth Table.All four address inputs have on-chip data latches which arecontrolled by the Strobe (ST) input. These latches aretransparent when Strobe is high but they maintain thechosen address when Strobe goes low. To facilitate easymicroprocessor control in large matrices a choice of threeindependent logic inputs (EN, CS and CS) are provided onchip. These inputs are gated together (see Figure 11) andonly when EN = CS = 1 and CS = 0 can an output switch beselected. This necessary logic condition is then latched-inwhen Strobe (ST) goes low.

SignalINSW1SW3SignalOUTSW2SignalGNDFigure 12. “T” Switch Arrangement

The two second level series switches further improvecrosstalk and help to minimize output capacitance.

The DIS output can be used to signal external circuitry. DISis a high impedance to GND when no channel is selectedand a low impedance to GND when any one channel isselected.

The DG535/536 have extensive applications where any highfrequency video or digital signals are switched or routed.Exceptional crosstalk and bandwidth performance isachieved by using n-channel DMOS FETs for the “T” andseries switches.

CSLatchA0LatchCSA1LatchA2LatchA3LatchSTn+pp-SubstrateGNDn+Decode LogicENGateSourceDrainFigure 11. CS, CS, EN, ST Control LogicBreak-before-make switching prevents momentary shortingwhen changing from one input to another.

The devices feature a two-level switch arrangement wherebytwo banks of eight switches (first level) are connected via twoseries switches (second level) to a common DRAIN output. In order to improve crosstalk all sixteen first level switchesare configured as “T” switches (see Figure 12).

With this method SW2 operates out of phase with SW1 andSW3. In the on condition SW1 and SW3 are closed with SW2open whereas in the off condition SW1 and SW3 are openand SW2 closed. In the off condition the input to SW3 iseffectively the isolation leakage of SW1 working into theon-resistance of SW2 (typically 200 Ω).

Figure 13. Cross-Section of a Single

DMOS Switch

It can clearly be seen from Figure 13 that there exists a PNjunction between the substrate and the drain/sourceterminals.

Should a signal which is negative with respect to thesubstrate (GND pin) be connected to a source or drainterminal, then the PN junction will become forward biasedand current will flow between the signal source and GND.This effective shorting of the signal source to GND will notnecessarily cause any damage to the device, provided thatthe total current flowing is less than the maximum rating, (i.e.,20 mA).

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DG535/536

Vishay Siliconix

DETAILED DESCRIPTION

Since no PN junctions exist between the signal path and V+,positive overvoltages are not a problem, unless thebreakdown voltage of the DMOS drain terminal (see Figure13) (+ 18 V) is exceeded. Positive overvoltage conditionsmust not exceed + 18 V with respect to the GND pin. If thiscondition is possible (e.g. transients in the signal), then adiode or Zener clamp may be used to prevent breakdown.The overvoltage conditions described may exist if thesupplies are collapsed while a signal is present on the inputs.If this condition is unavoidable, then the necessary stepsoutlined above should be taken to protect the deviceDC Biasing

To avoid negative overvoltage conditions and subsequentdistortion of ac analog signals, dc biasing may be necessary.Biasing is not required, however, in applications wheresignals are always positive with respect to the GND orsubstrate connection, or in applications involvingmultiplexing of low level (up to ± 200 mV) signals, whereforward biasing of the PN substrate-source/drain terminalswould not occur.

Biasing can be accomplished in a number of ways, thesimplest of which is a resistive potential divider and a few dcblocking capacitors as shown in Figure 14.

AnalogSignalINSV+An alternative method is to offset the supply voltages (seeFigure 15).

Decoupling would have to be applied to the negative supplyto ensure that the substrate is well referenced to signalground. Again the capacitors should be of a type offeringgood high frequency characteristics.

Level shifting of the logic signals may be necessary usingthis offset supply arrangement.

+ 12 VDG536GNDDAnalogSignalOUTDecouplingCapacitors+-3 VFigure 15. DG536 with Offset Supply

TTL to CMOS level shifting is easily obtained by using aMC14504B.Circuit Layout

Good circuit board layout and extensive shielding is essentialfor optimizing the high frequency performance of the DG536.Stray capacitances on the PC board and/or connecting leadswill considerably degrade the ac performance. Hence, signalpaths must be kept as short as practically possible, withextensive ground planes separating signal tracks.

+ 15 VAnalogSignalINC1+R2R1SV++C2DAnalogSignalOUT100 µF/16 VTantalumDG536GND100 µF/16 VTantalumFigure 14. Simple Bias Circuit

R1 and R2 are chosen to suit the appropriate biasingrequirements. For video applications, approximately 3 V ofbias is required for optimal differential gain and phaseperformance. Capacitor C1 blocks the dc bias voltage frombeing coupled back to the analog signal source and C2blocks the dc bias from the output signal. Both C1 and C2should be tantalum or ceramic disc type capacitors in orderto operate efficiently at high frequencies. Active bias circuitsare recommended if rapid switching time between channelsis required.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see http://www.vishay.com/ppg?70070.

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Legal Disclaimer Notice

Vishay

Disclaimer

All product specifications and data are subject to change without notice.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained hereinor in any other disclosure relating to any product.

Vishay disclaims any and all liability arising out of the use or application of any product described herein or of anyinformation provided herein to the maximum extent permitted by law. The product specifications do not expand orotherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressedtherein, which apply to these products.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by thisdocument or by any conduct of Vishay.

The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unlessotherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in suchapplications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resultingfrom such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regardingproducts designed for such applications.

Product names and markings noted herein may be trademarks of their respective owners.

Document Number: 91000Revision: 18-Jul-08

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